A semiconductor package having a semiconductor chip and a resin layer that covers the semiconductor chip has been known. For example, Japanese Laid-Open Patent Publication Nos. 2011-119502 and 2008-300854 describe a semiconductor package including an insulating layer that covers an active surface (circuit formation surface) and side surfaces of a semiconductor chip and a wiring structure that is stacked on the insulating layer and is electrically connected to the semiconductor chip.
A known method for such semiconductor packages is as follows. First, a support substrate is prepared. A semiconductor chip is mounted on the support substrate such that a surface of the semiconductor chip opposite to the active surface contacts the support substrate. An insulating layer is formed to seal the semiconductor chip. A wiring layer and an interlayer insulating layer are stacked on the insulating layer to form a wiring structure. Then, the support substrate is removed to complete the semiconductor package.